1. Field
Embodiments of the invention relate generally to a semiconductor memory device.
2. Background Art
Recently, semiconductor devices, such as the NAND-type flash memory, etc., are mounted on many electronic instruments. Such electronic instruments are required to have a wide variety of functions, which requires the mounted semiconductor devices to have large capacities, with a result that the memory elements are required to be highly integrated. To highly integrate the memory elements, the memory elements themselves must be shrank while the inter-element regions isolating the memory elements must be shrank.
For example, in the NAND-type flash memory, usually a memory transistor of the MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) structure including a floating gate electrode and a control gate electrode stacked is usually used as the memory element. In the NAND-type flash memory, a plurality of such memory transistors are serially connected, forming a NAND string. The NAND string has one end connected to a bit line via a selection gate transistor and the other end connected to a source line via another selection gate transistor. In each NAND string, the memory transistors adjacent to each other have the source/drain regions in common. (Refer to, e.g., FIG. 19 of JP-A 2006-351789). Accompanying the increase of the capacity of the NAND-type flash memory, the memory transistors themselves are required to be shrank, and at the same time, the inter-element regions isolating the memory transistors is required to be shrank.
However, shrinking of the inter-element regions tends to cause interferences between the adjacent memory transistors. For example, in the data programming operation of the NAND-type flash memory, the “programming error”, that data are erroneously stored in non-selected memory cells the data are not to be stored in, is occurred easily.